1. Field of the Invention
This invention relates generally to the field of signal synchronization systems and in particular to a signal synchronization system in which predetermined adjustments are made as a function of the time sample and the degree of dissimilarity between incoming and reference signals.
2. Description of the Prior Art
Signal synchronization systems for analog signals are well known in the art and, perhaps the best known systems are employed to control the tuning frequency for radio receivers. A phase lock loop circuit containing a voltage control oscillator would normally compare frequency with that of a master oscillator. Any drift of the voltage controlled oscillator frequency is detected by a phase comparator and the resulting error voltage provides a signal to adjust the voltage controlled oscillator and correct the frequency. The magnitude of the error signal is directly proportional to the phase difference between the signals and thus, synchronization may be maintained.
There have been many variations of prior art phase lock loop circuits which have been applied to processing incoming signals containing information in a digital format. The usual requirement in such systems is to synchronize a local clock with an external system clock so that correct decoding of digital information may be achieved. Such a system would be similar to a radio receiver tuning control circuit in which the voltage controlled oscillator is replaced by a local clock and phase adjustment circuit operating so that instead of modifying an oscillator's frequency, the local clock is adjusted to achieve time synchronization with the incoming signal.
As shown in the block diagram of FIG. 1, a data input line is supplied to a phase detector, which operates to determine the phase difference between the local clock and the incoming data signal. Such phase lock loop systems frequently include a transfer function circuit for modifying the effect of the error signal to achieve a predetermined functional relationship in the response of the system. The transfer function circuit is frequently designated as a weighting circuit and may include some time delay. The modified function is then applied to a sample and hold device which allows adjustments to be made to a system only at specific time periods. A separate timing circuit would normally determine when the modified adjustment will be applied to the phase adjuster to alter the local clock signal timing. The phase adjuster provides a recovered clock signal which is supplied to the phase detector.
The problems with such prior art circuits are several including the detection and distinguishing of digital signal levels which are usually in binary form, the effect of noise in the signal, and the cumulative effect of past adjustments. It is also difficult to determine the beginning and ending of a bit interval and the inclusion of the sample and hold feature is for the purpose of applying corrections only at selected intervals which ideally correspond to the edges defining a bit interval.
Another form of phase lock loop circuit which has been employed for synchronization utilizes differentiation techniques for the purpose of detecting the occurrence of edges of bit intervals. Normally, such systems rely in the detection of a repetitive .0. and 1 level signal pattern of sufficient length to allow the system to identify the occurrence of edges and to achieve synchronization of the local clock system with respect to the incoming bit edge sequence. The difficulties with the edge detection synchronization systems are that a .0. and 1 synchronization bit pattern must ordinarily be imposed on the incoming signal so that a sufficient number of distinct uniformly spaced edges can be provided to achieve synchronization; the presence of noise during the reception of this critical synchronization bit pattern can destroy the synchronization attempt; and simple drift in the local clock can result in a loss of synchronization.
Some additional prior art systems which attempt to reduce the problem by including a recovery circuit to maintain functioning if synchronization is not achieved within the time span of the repetitive .0. and 1 sequence or is subsequently lost have local clocks which can be synchronized in phase with broadcast system clocks, and thereby normally function is slave units, but can also function as a master clock in the event that synchronization is lost. The principal problem with such systems is that for digital information being broadcast in a synchronous format, having a local clock operating as a master clock can only be advantageous if the local clock has indeed been synchronized to the system clock and does not exhibit any drift with time and if the disruption interval is quite short.